Automatic test pattern generation (ATPG) for sequential circuits is an extremely expensive computational process. ATPG algorithms working on complex sequential circuits can spend many hours of central processing unit (CPU) time and still obtain poor results in terms of fault coverage. There are a number of factors that contribute to the difficulty of the ATPG process for sequential circuits. For example, it is generally necessary for an ATPG algorithm to use a model that includes an iterative array of time frames, where the number of time frames may be, in the worst case, an exponential function of the number of flip-flops (FFs) in the circuit. In addition, an ATPG algorithm may waste a substantial amount of time trying to justify illegal states. Furthermore, an ATPG algorithm typically must complete an exhaustive search for each target fault that is to be identified as untestable. Another difficulty is controlling and observing so-called “buried” FFs of the sequential circuit.
Because of the above-noted difficulties associated with sequential ATPG, complex sequential circuits are generally tested using design for testability (DFT) techniques, such as scan design, which significantly change the structure of a given circuit so as to make its buried FFs more controllable and observable in test mode. However, scan-type DFT techniques introduce delay penalties that result in performance degradation, and substantially increase circuit area overhead thereby increasing power consumption and decreasing yield. In addition, scan-type DFT techniques are not directly compatible with at-speed testing.
U.S. patent application Ser. No. 09/780,861, filed Feb. 9, 2001 and entitled “Sequential Test Pattern Generation Using Combinational Techniques,” which is incorporated by reference herein, describes techniques for performing ATPG for sequential circuits in a more efficient manner, so as to alleviate the problems associated with conventional ATPG, while also avoiding the problems associated with existing DFT techniques such as scan design.
Despite the considerable advancements provided by the techniques described in the above-cited U.S. patent application, a need remains for further improvements in the testing of sequential circuits using ATPG.